1. Field of Invention
The invention relates generally to the field of electronic circuit design. In one exemplary aspect, the invention relates to design of analog, mixed-signal and RF electronic circuits.
2. Prior Art Description
The process of designing electronic circuits for fabrication as Application Specific Integrated Circuits (ASICs), System-on-Chip (SOC) devices, or other types of Integrated Circuits (ICs) is well known in the prior art. Based on the type of logic or functions implemented, these circuits can be categorized as either being digital, analog or mixed-signal (circuits that are part-digital and part-analog) in nature. Examples of digital electronic circuits include at a very basic level flip-flops (FFs), or at a higher level the pipelined CPU of a microprocessor. Examples of analog circuits include the well-known phase-locked loop (PLL) or an operational amplifier (op-amp). Examples of mixed-signal designs include SOC implementations of modem ASICs that combine part-digital and part-analog functions.
In today's competitive marketplace, designers are under pressure to produce designs that are well-tested for successful fabrication, have quick turnaround times, can be migrated to a different fabrication process quickly (for example to a smaller feature size or different geometry), and that can be integrated with another design to fit on the same semiconductor die. Digital designs have benefited from improved Electronic Design Automation (EDA) tools that can automate much of this work.
In contrast, the design of analog or mixed-signal (AMS) circuits tends to involve more manual expertise to design portions of the circuit. Due to complex feedback loops that involve signal paths crossing between digital and analog domains, as well as other phenomena relating to non-linear dependence on geometry, changes in layout or geometry of analog circuit building blocks typically require extensive simulations to ensure that performance requirements and design constraints are met. This often results in lengthy design cycles where intervention by expert (human) designers is needed. AMS circuit design is therefore a recognized bottleneck in designing electronic circuits.
When designing AMS circuits, the physical properties of circuits such as device matching, parasitic coupling, and thermal and substrate effects must also be taken into account to ensure success of design. Nominal values of performance are generally subject to degradation due to a large number of parasitic couplings that are difficult to predict before the actual device layout is attempted. Overestimation of these degrading effects results in wasted power and area, while underestimation results in circuits not meeting their performance requirements.
Various prior art techniques exist for electronic circuit design and optimization. For example, in “DARWIN: CMOS opamp Synthesis by means of a Genetic Algorithm”, Kruiskamp et al., Proceedings of the 32nd Design Automation Conference, pp. 433-438, 1995, incorporated herein by reference in its entirety, a method is described to synthesize operational amplifiers (opamps). Both topology variations as well as changes in the dimensions of primitive devices are considered by the optimizer in minimizing the overall cost function. The method uses manually derived equations to relate optimization variables to performance measures, hence resulting in a very fast performance evaluation method. Composing this set of equations is typically only valid under restrictive assumptions which impose severe limitations on the search space. Moreover, this evaluation mechanism provides substantially inaccurate results compared to state-of-the-art device equations (e.g. BSIM device models). The synthesis method employs traditional genetic algorithms which deliver fair results for the example at hand, but which are less performing than more recent optimization approaches.
United States Patent Application Publication No. 2003/0009729 to Rodney Phelps et al., published Jan. 18, 2002 and entitled “Method for Automatically Sizing and Biasing Circuits”, and similarly “ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits”, M. Krasnicki et al., Proceedings of the International Conference on Computer-Aided Design, pp. 350-357, November 2001, both incorporated herein by reference in their entirety, describe a framework used to size a circuit topology towards a given set of performance specifications. Performances are evaluated based on circuit simulations. Solutions from previous optimization sessions are stored in a database. Information stored in this database steers the optimization engine in finding a solution to the design problem in a reduced amount of time. The way previous or intermediate solutions are stored in this database does not guarantee, however, that this set of candidate solutions covers a relevant portion of the performance space. Hybrid optimization techniques are applied where advanced “simulated annealing” techniques are combined with “hill-climbing” techniques. The optimization algorithm itself is not able to construct knowledge of the search space based on its experience.
Various other optimization techniques can be found in literature. These techniques may be broadly categorized as either deterministic approaches (i.e. gradient-based techniques which converge quickly to a (local) minimum), or stochastic approaches which are more robust towards finding the global optimum of a function. Given the complexity of the objective functions present in analog and mixed-signal circuit design problems, only stochastic optimization approaches are robust enough to be applied in an open and standardized framework. Hybrid approaches can be applied as well where the fast convergence properties of a deterministic optimization algorithm are combined with the robustness of stochastic approaches.
Examples of stochastic optimization algorithms are numerous. The following is only an exemplary short reference list of selected approaches: (i) simulated annealing; see, e.g., Kirkpatrick, S.; Gelatt, C. D.; and Vecchi, M. P. “Optimization by Simulated Annealing.” Science 220, 671-680, 1983; (ii) differential evolution; see, e.g., Storn, R. and Price, K., “Differential Evolution—a Simple and Efficient Adaptive Scheme for Global Optimization over Continuous Spaces”, Technical Report TR-95-012, ICSI, March 1995; and (iii) genetic algorithms; see, e.g., Chapter 4 in “Multi-objective optimization using evolutionary algorithms” by Kalyanmoy Deb, 1st ed., Wiley-Interscience series in systems and optimization, ISBN0-471-87339-X, each of the foregoing incorporated herein by reference in its entirety.
Recently, techniques have been developed that construct a stochastic model based on information obtained from previous experiments. This stochastic model is employed to suggest new candidate solutions to the optimization problem. A particular embodiment of this category of optimization techniques is presented in United States Patent Application Publication No. 2003/0055614 to M. Pelikan and D. Goldberg, filed Jan. 18, 2002 and entitled “Method for Optimizing a Solution Set”, incorporated herein by reference in its entirety. Deficiencies of this method include: (i) the inability to directly address continuous optimization variables (continuous optimization variables are translated back and forth into discrete variables), (ii) the inability to parallelize stochastic model construction over network of computers (models of sub-populations can be constructed in a parallel manner though). Also, the application of the disclosed techniques to analog and mixed-signal circuit design problems is not described or readily implemented.
U.S. Pat. No. 6,269,277 to del Mar Hershenson issued Jul. 31, 2001 and entitled “System and Method for Designing Integrated Circuits” discloses an optimization device in which circuit performances are formulated using so-called posynomial functions. Using this mathematical vehicle, fast optimization techniques are applied (geometric programs) to find the global optimum of the formulated design problem. Expressing circuit performances in a posynomial formulation is a topology and technology dependent task which tends to be elaborate.
U.S. Pat. No. 5,781,430 to Tsai issued Jul. 14, 1998 and entitled “Optimization method and system having multiple inputs and multiple output-responses” discloses a method and system for optimizing a steady-state performance of a process having multiple inputs and multiple output-responses. The method and system utilize a response surface model (RSM) module, and provide a unified and systematic way of optimizing nominal, statistical and multi-criteria performance of the process. The process can be, inter alia, a semiconductor manufacturing process or a business process.
U.S. Pat. No. 6,249,897 to Fisher-Binder issued Jun. 19, 2001 and entitled “Process for sizing of components” discloses a process for the sizing of components in a given componentry, in particular an electronic circuit, which fulfills a predetermined functionality defined in particular in marginal conditions. The individual components have characteristics which are essentially predetermined and are described in mathematical equations, and the components produce interactions based on their utilization in the given componentry or electronic circuit. The characteristics and/or interactions described by the equations are resolved by means of a computer, whereby the results obtained of the first resolved equations related to the required components are used in the resolution of additional equations. The solution and further treatment of those ranges of resolution possibilities which are without practical relevance to the sizing of the components in the given electronic circuit are not used.
U.S. Pat. No. 6,606,612 to Rai, et al. issued Aug. 12, 2003 and entitled “Method for constructing composite response surfaces by combining neural networks with other interpolation or estimation techniques” discloses a method and system for design optimization that incorporates the advantages of both traditional response surface methodology (RSM) and neural networks. The invention employs a strategy called parameter-based partitioning of the given design space. In the design procedure, a sequence of composite response surfaces based on both neural networks and polynomial fits is used to traverse the design space to identify an optimal solution. The composite response surface ostensibly has both the power of neural networks and the economy of low-order polynomials (in terms of the number of simulations needed and the network training requirements). The invention handles design problems with multiple parameters and permits a designer to perform a variety of trade-off studies before arriving at the final design.
United States Patent Application Publication No. 20030093763 to McConaghy published on May 15, 2003 and entitled “Method of interactive optimization in circuit design” discloses a method of interactively determining at least one optimized design candidate using an optimizer, the optimizer having a generation algorithm and an objective function, the optimized design candidate satisfying a design problem definition, comprises generating design candidates based on the generation algorithm. The generated design candidates are added to a current set of design candidates to form a new set of design candidates. The design candidates are evaluated based on the objective function so that design candidates can be selected for inclusion in a preferred set of design candidates. The current state of the optimizer is presented to a designer for interactive examination and input is received from the designer for updating the current state of the optimizer. These steps are repeated until a stopping criterion is satisfied.
United States Patent Application Publication No. 20030079188 to McConaghy et al, published on Apr. 24, 2003 and entitled “Method of multi-topology optimization” discloses a method of multi-topology optimization is used in AMS circuit design to address the problem of selecting a topology while sizing the topology. First, design schematics are manually or automatically selected from a database of known topologies. Additional topologies can be designed as well. For each candidate design there is associated a topology and a set of parameters for that topology. Analogously to the step of automatic sizing for a single topology, multi-topology optimization comprises optimizing over the entire population of design simultaneously while not requiring that all topologies are fully optimized. The multi-topology optimization step is repeated until one or more stopping criteria are satisfied. The sized schematic is then passed onto placement, routing, extraction and verification.
United States Patent Application Publication No. 20040064296 to Saxena, et al. published Apr. 1, 2004 and entitled “Method for optimizing the characteristics of integrated circuits components from circuit specifications” discloses a method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.
PCT application publication WO 02/103581 to McConaghy entitled “Top-down multi-objective design methodology” discloses a hierarchical sizing technique that decomposes a circuit X in all its components {Yi}. For each of these components Yi, samples are generated at the boundary of the feasible design space (the so-called Pareto-front) using an optimization technique. Synthesis of circuit X is again based on an optimization technique. In this latter optimization problem, the samples generated for components Yi are used as candidate solutions. This technique suffers from serious deficiencies, including the fact that generating samples for components Y and synthesizing circuit X comprise two completely distinct steps. As only a restricted set of discrete samples in the search space of components Y are suggested as candidate solutions, the method is severely restricted in its ability to find a solution to the synthesis problem of circuit X that approaches the optimum. Further, this technique cannot be combined with efficient yield estimation techniques due to the aforementioned use of discrete samples.
Based on the foregoing, it will be evident that while the prior art has in general recognized the utility of optimization approaches, it fails to adequately address many of the problems and intricacies associated with using this approach, especially in the context of AMS circuit design. Specifically, prior art design and optimization methods have comparatively limited algorithms for use in the AMS design process due to the complexity and the particular design issues associated with the latter. Furthermore, the prior art is largely unable to (i) directly address continuous optimization variables (continuous optimization variables are translated back and forth into discrete variables), or (ii) parallelize stochastic model construction over network of computers. Stemming largely from the foregoing limitations, prior art optimization techniques are also not sufficiently “evolutionary” such that a useful solution is converged upon rapidly.
What are needed are flexible methods and apparatus that are adapted to optimization within, e.g., the AMS context. Such improved methods and apparatus ideally would include powerful algorithms specifically adapted for use in the AMS context, the ability to handle continuous optimization variables, and parallelization of at least portions of the optimization process across two or more computational entities. Such improved methods and apparatus would further be compatible with hierarchical sizing methods, and be user-friendly so as to make the design process as a whole as efficient and easy as possible.